ARM and TSMC have had a joint agreement in place for several years to collaborate on R&D work and early validation on process nodes, and they’ve announced a major milestone in that process. As of yesterday, ARM is announcing that it has successfully validated a new 10nm FinFET design at TSMC.
The unnamed multi-core test chip features a quad-core CPU from ARM, codenamed Artemis, a single-core GPU as a proof of concept, and the chip’s interconnect and other various features.
This isn’t an SoC that ARM will ever bring to market. Instead, it’s purpose is to function as a validation tool and early reference design that helps both TSMC and ARM understand the specifics of the 10nm FinFET process as it moves towards commercial viability. One of the features that pure-play foundries like TSMC offer their customers are tools and libraries specifically designed to match the capabilities of each process node. Since each new node has its own design rules and best practices, TSMC has to tune its offerings accordingly — and working with ARM to create a reasonably complex test chip is a win/win situation for both companies. ARM gets early insight into how best to tune upcoming Cortex processors; TSMC gets a standard architecture and SoC design that closely corresponds to the actual chips it’ll be building for its customers as the new process node moves into production.
The slide above shows the gains TSMC expects to realize from moving to 10nm as opposed to its current 16nm process. To the best of our knowledge, TSMC’s 10nm is a hybrid process, but it’s not clear exactly what that hybrid looks like. Our current understanding is that the upcoming 10nm node would combine a 10nm FEOL (Front end-of-line) with a 14nm BEOL (Back-end-of-line, which governs die size). EETimes, however, reported in March that TSMC’s 10nm shrink would retain a 20nm minimum feature size, while its 7nm would deliver a 14nm minimum feature size (10/20 and 7/14, respectively). Either way, Intel is the only company that has announced a “true” 14nm or 10nm die shrink. (The degree to which this process advantage materially helps Intel these days is open to debate).
Two things to note: First, the top line of the slide is potentially confusing. The 0.7x reduction of power would be easier to read if ARM had labeled it “ISO Performance at 0.7x power.” Second, the performance gains predicted here purely as a result of the node transition are downright anemic. I don’t want to read too much into these graphs because it’s very early days for 10nm, but there’s been a lot of talk around 16/14nm as a long-lived node, and results like this are part of why — only a handful of companies will want to pay the extra costs for the additional masks required as part of the die shrink. TSMC has already said that it believes 10nm will be a relatively short-lived node, and that it thinks it’ll have more significant customer engagement for 7nm.
None of this means that ARM can’t deliver compelling improvements at 10nm — but the limited amount of lithography improvements mean a heavier lift for the CPU research teams and design staff, who need to find additional tricks they can use to squeeze more performance out of silicon without driving up power consumption.
As for when 10nm might ship, past timelines suggest it’ll be a while yet. TSMC has said it expects early 10nm tapeouts to drive sizeable demand starting in Q2 2017. While that’s a quick turn-around for a company whose 16nm only entered volume production in August 2015, the speed could be explained if the 10nm node continues to leverage TSMC’s existing 20nm technology. Bear in mind that there’s a significant delay between when TSMC typically ships hardware and when consumer products launch, particularly in mobile devices where multiple companies perform complex verification procedures on multiple parts of the chip.
Either way, this tapeout is a significant step forward for both ARM and TSMC, and 10nm will deliver improvements over the 16nm tech available today.
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